FIGS. 17 to 21 illustrate exemplary configuration and flowchart which is studied by the inventor. A configuration of the cache control used in the processor of the single thread system is illustrated in FIG. 17.
Reference sign 1000 illustrated in FIG. 17 denotes an instruction control unit, 2000 denotes a cache control unit, 2001 denotes a cache RAM, 2002 denotes a fetch port, 2003 denotes a store port, 2004 denotes a selection circuit provided in association with the fetch port 2002, 2005 denotes a selection circuit provided in association with the store port 2003, 2006 denotes a check circuit provided in association with the fetch port 2002, 2007 denotes a check circuit provided in association with the store port 2003, 2008 denotes a check circuit provided in association with the fetch port 2002 and the store port 2003, 2009 denotes a check circuit for a discharge request, 2010 denotes an AND circuit, and 2011 denotes a priority control circuit.
As illustrated in FIG. 17, memory access requests from the instruction control unit 1000 are once held in the fetch port 2002 having plural entries present in the cache control unit 2000.
The access requests are allocated to the respective entries of the fetch port 2002 according to instruction order. However, in a processor that processes memory accesses in out of order, the access requests are read out in random order and subjected to cache access processing. When the cache access processing is completed, the entries of the fetch port 2002 are released.
An oldest entry among effective entries of the fetch port 2002 is indicated by a FP-TOQ (Fetch-Port-Top-Of-Queue) generated by a not-illustrated control circuit.
When a memory access request from the instruction control unit 1000 is a store request, the request is held in the fetch port 2002 and, at the same time, held in the store port 2003.
When the store request is processed, if there is no problem in address translation processing, sequence guarantee of access request and the like, the entry of the fetch port 2002 is released at that point. Thereafter, the store port 2003 manages store processing in the cache RAM 2001. When the store processing is completed, entry of the store port 2003 is released.
An oldest entry among effective entries of the store port 2003 is indicated by a SP-TOQ (Store-Port-Top-Of-Queue) generated by a not-illustrated control circuit.
As one of memory access requests from the instruction control unit 1000, there is an atomic load store request by a CAS instruction or the like (hereinafter referred to “fetch and store request”).
Reference and update of relevant data by other instructions have to be prohibited in a period from load execution of this fetch and store request until store execution of this fetch and store request.
Therefore, when the fetch and store request accesses data A, it is necessary to provide the following conditions:
(a-1) processing of the fetch and store request is suppressed until processing of all requests for accessing the data A prior to the fetch and store request are completed;
(a-2) processing of a request for accessing the data A after the fetch and store request is suppressed until the processing of the fetch and store request is completed; and
(b) discharge of the data A from the cache RAM 2001 is suppressed in a period from the start of the processing of the fetch and store request until completion of the processing,
to guarantee exclusive control in the processor for fetch and store target data according to the conditions (a-1) and (a-2) and guarantee exclusive control between processors in a multiprocessor configuration according to the condition (b).
Therefore, concerning the condition (a-1), as illustrated in flowcharts of FIG. 18 and FIG. 19, the start of the processing of the fetch and store request is guaranteed by permitting, using the check circuits 2006 and 2007, the start if the entries of the fetch port 2002 and the store port 2003, in which the fetch and store request is held, are the FP-TOQ and the SP-TOQ.
In the flowchart of FIG. 18, it is assumed that access requests (request#m=request#n) stored in an entry FP#m (an m-th entry) of the fetch port 2002 and an entry SP#n (an n-th entry) of the store port 2003 are processed according to selection processing of the selection circuits 2004 and 2005.
Next, concerning the condition (a-2), as illustrated in flowcharts of FIG. 18 and FIG. 20, the start of processing of an access request other than the fetch and store request is guaranteed by suppressing, using the check circuit 2008, the start of the processing when an entry of the fetch and store request is present in a period from an entry of the FP-TOQ until an entry of the fetch port 2002 in which the access request is held and suppressing the start of the processing when, although such an entry is not present, the access request coincides with target data of a prior store request held in the store port 2003.
Concerning the condition (b), as illustrated in a flowchart of FIG. 21, the start of discharge processing of data from the cache RAM 2001 is guaranteed by suppressing, using the check circuit 2009, the start of the discharge processing when an entry of the SP-TOQ is the fetch and store request.
In the processor of the single thread system, exclusive control processing requested in execution of the fetch and store instruction is realized according to such a configuration.
On the other hand, in the processor of the SMT system, since exclusive control among threads is necessary, cache control used in the processor of the single thread system configured in this way cannot be directly used.
However, under the actual circumstances, there is no disclosure to the present concerning according to what kind of configuration the exclusive control processing requested in execution of the fetch and store instruction is realized when the processor of the SMT system is mounted.
In future, manufacturers need to construct a cache control technique having a new configuration for realizing the exclusive control processing necessary in processing the fetch and store instruction such as the CAS instruction when the processor of the SMT system is mounted.
As a technique related to the present invention, in Patent Document 1 described below, an invention for realizing guarantee of consistency of execution order for readout and writing of shared data among threads in the processor of the SMT system is described.    Patent Document 1: International Publication WO2004/068361